Digital signal processing (DSP) blocks are used for implementing high-speed multiplication functions. DSP blocks in programmable devices are increasingly used in applications such as video and image processing. Often, DSP blocks perform not only multiplication, but also multiplication with addition, subtraction or accumulation. For instance, the sum of multiplication results is useful in applications such as finite impulse response (FIR) filtering and discrete cosine transforms (DCTs). As such, DSP blocks in integrated circuits (ICs) or programmable devices usually include at least a multiplier and an accumulator to perform all the required functions.
Generally, additional DSP functions like addition, subtraction and accumulation are implemented after the multiplier. Dedicated digital signal processing (DSP) blocks usually have embedded multiplier-accumulator blocks. But for lower-end devices, these DSP blocks may only have embedded multiplier blocks without a built-in accumulator. These devices can still perform normal multiplication. However, if accumulation of a series of multiplication results is needed, then other resources in the devices may need to be used. For instance, memory blocks may be used as look-up tables (LUTs) to store multiplication results. This would inevitably result in slower calculation speeds as compared to having a built-in accumulator.
Therefore, it is desirable to have a built-in accumulator function within the multiplier block even for lower-end devices. Having a built-in accumulator inside the multiplier block also enables the multiplier to effectively perform various different modes, e.g., multiplication, accumulation and multiplication followed by addition. It is within this context that the invention arises.